Product Updates in 5.0
Products and tools included in this document for the 5.0 release are listed below:
Linux Port Product Information
Cadence Analog Design Environment
Cadence AMS Design Environment and Design Simulator
CDSDoc, Cadence Online Documentation
DFII to Cadence Chip Assembly Router Translation
PIPO Stream In and Stream Out Interface
Technology File and Display Resource File
Virtuoso Relative Object Design (ROD)
Linux Port Product Information
The following products and tools for the IC 5.0 release are not available on Linux:
Coefficient Generator
The Coefficient Generator calculates parasitic capacitance extraction coefficients for the Silicon Ensemble® products, the Diva® verification product, the Dracula® verification products, and the Cadence® HyperExtract interconnect parasitic extractor. This product is unavailable on Linux.
Modelwriter
Modelwriter automatically generates Verilog®-A models. Modelwriter is currently not available on Linux.
Strokes Editor
Certain VHDL Functionality
The VHDL-IN and VHDL-Toolbox products are currently not available on Linux. The GUI is available but is not supported. Cellview-to-cellview functionality for VHDL views is not supported.
NeoCell Setup Wizard
NeoCell, a product developed by Neolinear, enhances efficiency and ease of adoptability into the Cadence IC design solutions by providing rapid design of complex analog, mixed-signal, and SoC's. The NeoCell Setup Wizard, a new Cadence tool, streamlines this process but is currently not supported on Linux.
Cadence Analog Design Environment
The 5.0 release of the Cadence® Analog Design Environment includes the following enhancements.
New tools that provide
Improved yield analysis on circuits that can be modeled by polynomials (response surface methodology)
Improved analysis to determine DC offsets resulting from mismatch of all devices in a circuit
Revised Monte Carlo analysis
New algorithm for stability analysis to determine accurate loop gain and phase and gain margins
Improved distributed processing that supports LSF 4.01 and contains precise error messages
New graphical user interface for corners analysis, including more compact tables
New Direct Plot form to probe waveforms from the schematic; added waveforms now appear as you click each node; additionally, functions and modifiers are provided for all Spectre® analyses
Enhanced Calculator provides a special function for superposition of periodic waveforms; the improved
printvsfunction works with parametric dataMixed-signal parasitic simulation (MSPS) flow supports Assura® verification tools, which can be a replacement for the DIVA® products.
Cadence AMS Design Environment and Design Simulator
The 5.0 release of the Cadence AMS Design Environment and Simulator includes these features:
AMS Designer is now fully supported on the RedHat Linux operating system.
VHDL-AMS design units are now supported in AMS Designer along with Verilog-AMS modules and Spectre netlists.
The AMS environment has been enhanced to support GUI driven model file selection and netlisting into temporary libraries to support read-only reference libraries that do not have existing Verilog-AMS netlists.
The AMS Simulator now supports save-restart, making it possible for designers to perform efficient "what if" analyses using saved simulations.
The AMS Simulator now supplies a new set of default connect modules that improve simulation speed. The connect modules also support bi-directional connections for flexible mixed-signal simulation.
SimVision is the new simulator environment, featuring a unified design browser with improved access to simulator control buttons. SimVision also supports a new "walk-up" connection use model.
Cadence Hierarchy Editor
The 5.0 release of the Cadence Hierarchy Editor includes the following enhancements:
Occurrence binding
Stop points
Bind-to-open attribute
Library lists at the cell and instance level
Legend dialog box
Cadence SKILL Language
Over 300 new and documented SKILL functions are included in the 5.0 release.
CDSDoc, Cadence Online Documentation
Version 2.0 of CDSDoc includes these new features.
Easier navigation to the topic you want by using the table of contents for each document from the Library window.
New Edit - Preferences commands that
Control whether the document opens in a new browser window or reuses the current active browser window
Set the Search results page to open in a new browser window or to reuse the current browser window
Set a timeout for the documentation system
Ability to add your documents to the Search index.
Ability to specify which Cadence hierarchies CDSDoc should use.
DFII/NeoCell v3.2 Integration
For users of the NeoCell automatic place-and-route software for analog/mixed-signal physical synthesis, the IC 5.0 with NeoCell v3.2 flow is more closely integrated than in previous releases. The NeoCell software saves changes made during its execution directly to the Virtuoso layout you specify on the DFII database. Additionally, NeoCell returns its module generators to DFII as parameterized cells; DFII supports modification and specification of module generators as Pcells.
For details about new features in NeoCell v3.2, see the Neolinear NeoCell v3.2 Release Notes, which are supplied with the Neolinear documentation.
DFII to Cadence Chip Assembly Router Translation
The 5.0 release includes the following translation enhancements.
The new predefined device class,
cdsViaDevicecan used to create minimum area rules (MAR) compliant vias for stacked via topologies in the Cadence® chip assembly router. Once defined in your technology file, you can use the cdsVia to create symmetrical vias in the router. The enclosure values and direction parameters are mapped to theva_config_descriptor,cut_overhang,x_overhang, andy_overhangvalues. Upon return from the router they are then mapped to a pcell variant, if one exist, otherwise a new variant will be created.The mapping of technology file class rules to the Cadence chip assembly router (version 11.0.09 or higher) has been enhanced to support special design rules for nanometer processes (feature size of 90 nm and below).
maxWidth, in thephysicalRulesclass,spacingRulessubclass, allows you to specify the maximum width of any single wire.
viaSpacing, in thephysicalRulesclass,tableSpacingRulessubclass, allows you to specify larger than minimum spacing between via cuts.
minSpacing, in thephysicalRulesclass,tableSpacingRulessubclass, allows for different minimum spacing between objects based on design context, as opposed tospacingRules,minSpacing, which applies the same minimum spacing rule in all cases.
prMaxStackViassubclass, in theprRulesclass, allows you to specify the maximum number of stacked vias allowed within a specified layer range.
LEF/DEF Interface
Version 5.4 of the LEF/DEF interface contains these enhancements.
LEF/DEF can be started in context with Design Framework II using
layout.exe,layoutPlus.exe,icca.exe,icfb.exe, ormsfb.exe. LEF/DEF is no longer dependent on the Preview executable.Support of LEF 5.3, 5.31, and 5.4 and DEF 5.3 and 5.4.
Public SKILL functions to read/write LEF/DEF.
Read LEF command updates the Design Framework II technology file to reflect rule changes.
LEFIn appends the abstract information within an existing layout view.
LEF automatically sets offset value to -1.0 if offset is not specified in the LEF file.
Several syntax additions including
Second
RANGEargument to theLAYERstatement
SPACERandANTENNACELLoptions to theCORE CLASSargument in the LEFMACROsectionEnhanced geometry spacing statements, spacing rules, and length threshold range.
PIPO Stream In and Stream Out Interface
In the 5.0 release, PIPO is bundled with Virtuoso Layout Editor and Virtuoso XL Layout Editor and includes these enhancements.
Performance improvements to
Master opening
Hierarchy handling
Pcell processing
Layer mapping
Stream processing
Mosaic processing
Ability to attach an existing technology library to the target library during Stream In.
Improved error message contents with expanded descriptions, documented in the PIPO Messages chapter of the Design Data Translator's Reference manual.
Preview Abstract Editor
In the 5.0 release of Preview Abstract Editor, the Create Obstruction command allows you to draw obstructions on contact and via layers such as cont, via, and via2.
Spectre Circuit Simulator
The enhancements to the Spectre Circuit Simulator in the 5.0 release include the following.
Improved stability analysis that accurately and quickly calculates phase margin and gain margin, and the corresponding margin frequencies.
DC Mismatch Analysis efficiently calculates the dc operating point deviation of your circuit (current or voltage) and displays the devices responsible for that deviation.
Model name passing enables you to pass string parameters into subcircuits to specify model names.
Measurement capability in the Spectre circuit simulator is now based on the Spectre Measurement Description Language, SpectreMDL. It supports a large number of expression types designed to address a wide variety of characterization activities.
Automatic stopping allows you to save an enormous amount of simulation time if you are interested in just the SpectreMDL expression output values.
The Search function allows for efficient measurements of metrics such as setup and hold time.
Multiconductor transmission line model models a transmission line that includes an arbitrary number of conductors.
Normalized Sensitivity Analysis removes the dependence of results on the magnitude of the design parameter inputs.
New and updated models include bsim4, bsimsoi version 2.2, hicum version 2.1, mextram, and mos1100.
The Spectre simulator can specify different netlist readers through the command line option
spp.
Spectre RF Simulation option
The 5.0 release of the Spectre RF Simulation option includes these enhancements.
MIC-Periodic Steady State (MIC-PSS) Analysis
SpectreRF core analysis PSS and the small signal analyses Periodic AC (PAC), Periodic Transfer Function (PXF), and Periodic noise (Pnoise) now use only the multi-interval Chebyshev polynomial, which substantially increases the capacity of the SpectreRF simulator.
Quasi-Periodic Small-Signal Analyses: QPAC, QPXF, and Quasi-Periodic S Parameter (QPSP)
Pdisto analysis is now called Quasi-Periodic Steady State (QPSS) analysis. Quasi-Periodic small-signal analyses follow the QPSS analysis. The other quasi-periodic small signal analyses QPAC, QPXF, and QPSP have been added. These small-signal extensions to QPSS enable you to perform numerous types of simulations and diagnose circuits.
Error Preset
This enhancement will enable you to get very good RF analysis convergence and performance on most circuits with "out of the box" settings by using the new conservative, moderate, or liberal settings. These analyses settings work without any modifications for most circuits and applications.
Line Model Generator
A new model, mtline, is available in the transmission line model generator. This model allows you to model multiconductor lossy or lossless transmission lines, coplanar lines with very high level of flexibility when you define the lengths, widths, heights, and thicknesses of multiple transmission lines. New also is the ability to take into account the dielectric loss of the substrate when modeling the transmission line.
The transmission line model generator generates two models:
An RLCG model of the mtline that can be used only with non-RF analyses
A lumped macro model that can be used with RF analyses like PSS and QPSS
The LMG tool can be started while running the mtline model in the analog design environment. This lets you view the transmission lines while you are working on them.
Substrate Coupling Analysis (SCA)
Increased capacity enables SCA to handle a large number of substrate ports at a reasonable cost. This high-capacity SCA will enable you to create the substrate model of an entire production chip. A new algorithm, based on graph theory, is capable of handling a very large number of substrate ports. The time needed to generate the reduced model of the substrate is proportional to the number of substrate ports.
Probing capability has been added.
Technology File and Display Resource File
The 5.0 release includes these enhancements to the technology file.
The graphical user interface used for accessing, editing, and loading technology files now contains the technology file manager (
techManager), which is accessible both through the CIW, and as a standalone application.A new
layerRulessubclass,layerFunctions, lets you assign functions (cut,li,metal,ndiff,nplus,nwell,pdiff,poly,pplus, orpwell) to layers.Two new subclasses allow specification of lookup tables for conditional determination of rules.
A table is defined as having a rule name (for example,
minWidth) and applies to one or two layers or layer-purpose pairs. It can be one- or two-dimensional and is indexed by numeric or string data. Indices can be numerics or strings.The
techManagerprovides GUIs to define and edit rules tables.A new Devices class subclass,
cdsViaDevice, allows declaration of the new Cadence-predefinedviadevice type.In the
prRulesclass, theprTurnViaRulessubclass is eliminated; turn vias are now specified in theprViaRulesorprGenViaRulessubclass.The
prRulesclass contains a new subclass,prMaxStackVias, which allows you to specify the maximum number of stacked vias allowed within a specified layer range.The
prGenViaRulessubclass now allows a choice of specifying either a direction and minimum overhang or enclosure overhang data.Properties can now be specified in the
prViaRules,prGenViaRules, andprNonDefaultRulessubclasses of theprRulesclass.New SKILL functions allow updating of the
prMaxStackViassubclass:
techSetPrMaxStackViaallows you to add one set of maximum stacked vias data to the subclass
techSetPrMaxStackViasallows you to replace the entire subclass with new stacked vias dataNew GUI functions on the Layer Rules form allow specification and editing of layer functions.
New GUI functions on the Physical Rules and Electrical Rules forms allow access to the new Edit Spacing Rules Table and Edit Electrical Rules Table forms for specifying and editing spacing rules tables and electrical rules tables.
The new PR Rules form allows specification and editing of Place and Route subclasses. You can edit the following through the GUI:
Routing Layers
Via Types
Routing Pitch/Offset
Master Slice Layers
Stack Vias
Via Rules
Gen Via Rules
Nondefault Rules
The Layer Purpose Pair Editor form, accessed through the Edit Layers button in the Technology File Tool Box form, now displays a maximum of 50 layer-purpose pairs at a time. Next and Previous buttons allow paging through all of the available layer-purpose pairs.
New Check Technology File results are displayed when you run a check on a technology file for conformance to application requirements. The report can be saved to a file.
The 5.0 release includes these enhancements to the display resource editor.
The GUI for accessing, editing, and merging display resource files now contains the Display Resource Manager (
displayManager), which is accessible both through the CIW and as a standalone application.An HI 24-bit color panel, which increases the number of colors previously available with the 256-color, 8-bit color panel.
The ability to search for a display packet or layer-purpose pair by name and locate it in the Packet or Layers list box on the DRE form.
A new form that allows you to add a new display packet to the display resource file.
Virtuoso Compactor
In the 5.0 release of the Virtuoso Compactor, the Inhibit Wire Merge command is included in the Constraints menu. This command handles the no-merge mode of user-specified nets.
Virtuoso Constraint Manager
The 5.0 release of the Virtuoso Constraint Manager, previously called the Constraint Editor environment, includes these enhancements.
Completely revised engine and new database schema for storing constraint data in cellviews including constraint, axis, cluster, and net-class.
Spreadsheet-style GUI for consistent presentation of constraints and their status.
New SKILL API to consistently handle all constraint types and logically delineate constraint data types into specific sections. All current Constraint Manager clients are updated to work with the new API.
Usability improvements include
Virtuoso Layout Editor
The 5.0 release of the Virtuoso Layout Editor includes the following enhancements.
New Create Contact form for cdsVia:
Once you have defined cdsViaDevice in your technology file, you can place these vias using the Create Contact form. When you choose a predefined cdsVia in the Contact Type field, the form expands to allow you to change the via parameters. You can edit placed vias using the Edit Properties form.
New Environment Variables for cdsVia:
cdsViaXcutSpacing
cdsViaYcutSpacing
cdsViaLayer1XEnclosure
cdsViaLayer1YEnclosure
cdsViaLayer2XEnclosure
cdsViaLayer2YEnclosure
cdsViaLayer1Direction
cdsViaLayer2Direction
cdsViaStackedVias
cdsViaResetXYCutSpacing
cdsViaResetLayer1XYEnclosure
cdsViaResetLayer2XYEnclosure
cdsViaResetLayerDirection
cdsViaResetOriginNew SKILL functions for cdsVia:
New User Defined Layers
Previously, user defined layers were from 0 to 127, with 128 defined as the null layer. Currently, user defined layers are from 0 to 194, with 195 defined as the null layer.
Performance improvements in these areas:
Design Framework II Display & Rapid Rendering functionality contains a new draw engine mechanism that uses layer-purpose pair priority to render data. Using the layer-purpose priority from highest to lowest provides a context for filtering obscured data. This procedure reduces the amount of data traversed and drawn.
Find Marker, Delete Markers, and Search and Replace use more efficient hierarchy traversal
Load and Open have improved Save As and batch operations
Pcell has more efficient parameter evaluation and new
dbfunctions for shape arraysUnDo and ReDo have improved menu response and trigger efficiency
Search now functions on
Text display
Pins
Library name in an array search
ROD name in a label, path, polygon, rectangle, any shape, and text display search
Move, Copy, and Stretch include a Delta X Y option.
Create Shape Pin includes circular pin.
The Create Pins From Labels form includes a sym pin option to create symbolic pins.
The Create Pins From Labels form includes an Apply button.
The layer selection window (LSW) now displays the full layer-purpose name when the cursor rolls over it. The full name display can be turned on and off in the new LSW Option form.
Delete can delete path segments and net interconnect.
Tree displays the stop level and can run in read-only mode.
Mark Net runs in both read-only and edit modes and can start at any level of your circuit.
Path stitching supports a more complete choice of contact types.
Sticky Net, a component of the Virtuoso XL connectivity-driven methodology, is available in the Layout Editor Options form.
The new
leDefineMPPTemplatefunction lets you use a text editor to define multipart path (MPP) templates in ASCII files. It also provides the syntax the system uses to save MPPs to ASCII files from the Create Multipart Path form.New environment variables include
Virtuoso Relative Object Design (ROD)
The 5.0 release of Relative Object Design includes the following enhancements.
Values in the Create Multipart Path form that define a multipart path (MPP) can be saved as a template in an ASCII file.
The
rodCreateRectfunction was enhanced to let you create multipart rectangles (similar to creating multipart paths) by specifying arrays of unnamed rectangles.The new SKILL function
rodFillBBoxWithRectslets you fill an area with as many rectangles as will fit. You could use this function to define contacts and vias, among other things.To get the best performance, especially when creating a very large number of rectangles, you can choose one of the three functions below, depending on whether you want to create unnamed rectangles, arrays of unnamed rectangles, or named rectangles. Regular, unnamed database shapes require less overhead, resulting in faster performance.
The
dbCreateRectfunction creates a single rectangle that is a regular, unnamed database shape (without ROD attributes).The
rodFillBBoxWithRectsfunction creates a one- or two-dimensional array of unnamed rectangles that have no ROD attributes.The
rodCreateRectfunction creates named rectangles with ROD attributes.
Virtuoso Schematic Composer
The 5.0 release of the Virtuoso Schematic Composer includes the following enhancements.
All net expression properties that can be set on an instance can be located using Edit - Net Expression - Available Properties.
All evaluated results of net expressions below an instance can be located using Edit - Net Expression - Evaluated Names.
Virtuoso XL Layout Editor
The 5.0 release of the Virtuoso XL Layout Editor includes the following enhancements.
Performance improvements in both the connectivity extractor and binder.
Expanded netlist-driven flow supporting SPICE (3f4) netlist format and automatic folding and chaining of transistors with Gen from Source.
Gen from Source supports
Incremental updating of pin information that results in significant performance improvement for designs with large number of pins
Folding independent of chaining
Note: If you edit component types, (used for folding and chaining), created in IC 4.4.6, using an editor in IC 5.0.0 or later, the data will be saved in a new format that is incompatible with 4.4.6.
Save and load Virtuoso custom placer data including pin placement data, placement style, and partitioning information
Pick from Schematic supports
Options for pin generation when pins are selected in the schematic including size, layer, I/O type, access direction, and label. Also, folding is independent of chaining.
Ability to select and place individual elements at lower levels in a schematic hierarchy
Align has a new user interface and supports
Both pre- and post-selection of components with the Selection Mode option
Alignment of components using a selected reference point of a component's BBox or Layer BBox
Multiple values for spacing or pitch between components
Sorting of components using different criteria for priority
Alignment of component clusters to a given reference
Alignment of different layers between reference and target objects
Clone has an enhanced user interface and improved use model. Clone supports
Multiple cell views, both schematic and layout
Hierarchical, permuted, and chained devices
Global search of the entire schematic to find matching objects for targets
Disregard of parameter mismatches or limited search to exact parameter matches
The Engineering Change Order (ECO) mode commands have been enhanced in these areas.
Update Components and Nets, with the folding and chaining options on, maintains existing placement.
Update Layout Parameters supports folded devices.
The new Create Device Correspondence option allows you to create a correspondence between a schematic and a layout that have mismatched instances and pin names. This option works with both schematic and netlist with particular consideration to legacy designs. With this option you can
Create correspondence between unmatched schematic stop points and unmatched layout instances and pins
Confirm your layout is LVS correct by construction with matching layout masters
Derive device connectivity from instance and pin assignments when you set the correspondence
Use Computer Aided mode to perform incremental LVS
The new
lxRemoveDeviceproperty, used in conjunction with thelvsIgnoreproperty, allows shorting of parasitic devices in the schematic during layout generation without flagging a mismatch between schematic and layout. This property is compatible with Diva and Assura verification tools, and the Cadence Analog Design Environment. With these properties you can
Use a flat or hierarchical schematic or netlist that includes multiterminal parasitic devices
Provide a SKILL function to determine the threshold or cutoff value for shorting a parasitic device
Usability improvements include
Ability to specify
permuteRuleoutside of CDF whenCDS_Netlisting_Mode=AnalogMapping capability in schematic-driven flow, similar to netlist-driven flow
S-Factor works with three or more terminal devices causing any non-series terminal to short for all the devices in the series
Support of hierarchical m-factor, off-grid folding prevention, pseudo-parallel chains longer than two devices, and filters for errors and warnings from Check Against Source
Wire Editing in Virtuoso XL
The Virtuoso XL wire editing functionality is being implemented in a phased approach. Polygon editing and more extensive rule support will be supported in subsequent releases. The 5.0 release introduces the first phase of this effort and includes these new features.
Interactive routing, which supports online design rule checking through technology file process rules. With interactive routing you can
Route single and multiple paths, change layers, and place vias
Push routes and components while maintaining clearance rules
Match pin and wire widths
Editing commands, which let you
Stretch paths and push routes and components while maintaining clearance rules
Reshape wires and push routed paths and components
Copy existing routes, including vias, to unrouted connections that have similar lengths and topology
Compact routes within a selected area
Eliminate notches and remove extra bends in selected paths
Checking for design rule violations, which you can use to
Interactively check for rule violations
Control which rule violations and pin data problems are checked, graphically marked, and included in reports
Set specific rules inside regions and check areas inside the regions for violations
Support for a subset of the custom router rules. You can
Set constraints and definitions by loading
.dofilesOverride technology file rules by loading rules files
Routing reports, which you can use to display information about unconnects, conflicts, rule violations, number of pins, number of components, vias, and length for each routing layer
Route options, which let you control the routing environment and routing style
Custom Placement in Virtuoso XL
The Virtuoso Custom Placer is now a feature in the Virtuoso XL Layout Editor, product number 3000. License 3100 is no longer needed in a 5.0 hierarchy. The following enhancements are included in the 5.0 release.
Placement Style is able to combine standard cells and CMOS transistors in the same row.
Design Partitioning can
Perform assisted row generation on any individual partition for incremental layout generation on any targeted set of devices
Display logical partition information by flat instances, hierarchical instances, component types, source master, and target master
Sort and display partitioning information based on what you want to view or edit
Target individual partitions or regions within partitions for estimation and assisted row generation
Perform cross-selection, which links the partitioning form, the Virtuoso XL Layout Editor, and the Virtuoso Schematic Composer
Load partitioning information from a template file
Placement Planning can
Target individual partitions for assisted row-generation operations
Load either a selected partition or the entire partitioning row data, which was previously captured within a template file
Automatically cutback placement area allowing for pin to row separation
Expand both the partition and/or region to accommodate devices either horizontally or vertically
Generate missing devices and retain constrained devices with new layout- generation options
Separate subforms for Region, Row, Rail, and Components attributes
Set placement grids within standard cell and mixed row definitions
Control chaining, stacking, and chain size parameters from within the Placement Planning form
Pin Placement can
View all pin data within the design at the same time rather than pins on a specific boundary only
Cross-select between layout and schematic with the Link to Layout command
Place Pins As In Schematic arranges pins in your layout to match the relative positions of pins in your schematic.
Changing Pins into Rails converts any I/O pin into either a horizontal or vertical rail. The pin is stretched from any boundary edge to the opposite boundary edge.
User-Movable after Placing includes an addition to the Fix after Placing constraint. This constraint capability is for pins within the fixed constraint. Once this constraint is attached, it allows you to manually move a pin within the layout to any position as if no constraint were present. However, the automatic placement feature remembers the current or last position and will not move the pin.
Template Data loads pin information for re-use.
Synchronized Pin Placement checks that the pin constraint data in the Constraint Manager matches the pin constraint data in the Pin Placement form.
Automatic Placement Run Time includes these enhancements:
Faster and more efficient mixed design style runs due to improved checking procedures
Recognition of all object types within devices by layer rules
Automatic substrate contact insertion for standard cell designs available when insertion components and min/max spacing are specified
Improved placement engine that recognizes and aggressively abuts devices and device chains with serial connections enabling compact device chains
Separate controls for spacing devices within and between rows
Template writes out and reads in incremental prBoundary; I/O pin locations; and constraints, row, and partition information to an ASCII template file: Any part of the file can be read into a different design for reuse
Usability improvements include
Environment Variables in Virtuoso XL
A total of 163 public variables are documented in the Virtuoso XL Layout Editor User Guide. This includes106 Virtuoso XL and 57 Wire Editor variables. The following tables list pertinent changes about the variables.
*For internal use only-changing these variables may cause problems with the software
WaveScan
The WaveScan simulation results-processing application is offered standalone in this release. It consists of an integrated set of powerful postprocessing tools, including
A Results Browser, which displays signals in the hierarchical arrangement of your design
A Graph tool, which helps you represent your simulation data graphically
A Table tool for displaying scalar data
A Calculator, which uses the language and syntax of SpectreMDL to help you build expressions that address the needs of a wide variety of analysis types
Data ranging, which makes it easy to use a very large dataset efficiently by opening just the portion of the dataset you need.